Circuit arrangement for interference-free recognition of the zero crossings of sine-like signals

ABSTRACT

An arrangement for recognizing zero crossings of sine-like signals in the presence of interference utilizes a bistable flipflop circuit which is capacitively coupled to receive input signals from a differential amplifier having a pair of inputs which are symmetrical with respect to ground. The coupling capacitors and the bias resistors of the flip-flop circuit provide a switching threshold which is smaller during a succession of useful signals and during receipt of individual interference signals. The flip-flop circuit feeds impulse generating means to provide correctly timed, for example, rectangular signals.

United States Patent [191 Haass et al.

[ 1 CIRCUIT ARRANGEMENT FOR INTERFERENCE-FREE RECOGNITION OF THE ZEROCROSSINGS OF SINE- LIKE SIGNALS [75] Inventors: Guenther Haass; DieterReinhardt,

both of Munich, Germany [73] Assignee: Siemens Aktiengesellschaft,Berlin and Munich, Germany [22] Filed: AprilS, 1971 [21] Appl.No.:131,353

[30] Foreign Application Priority Data April 24, 1970 Germany ..P 20 20187.0

[52] US. Cl. ..328/150, 307/235 R [51] Int. Cl. ..II03k 5/20, H03k 17/30[58] Field of Search ..307/235; 328/150, 11 S [56] References CitedUNITED STATES PATENTS Mack ..307/235 X Lynes ct al. ..307/235 X 1 Feb.13, 1973 OTHER PUBLICATIONS L. M. Koch, Zero-Crossing Detector and PulseGenerator IBM Technical Disclosure Bulletin, Vol.

12, No. 8, January, 1970, pg. 1,177

Primary ExaminerJohn Zazworsky Attorney-Hill, Sherman, Meroni, Gross &Simpson [57] ABSTRACT An arrangement for recognizing zero crossings ofsinelike signals in the presence of interference utilizes a bistableflip-flop circuit which is capacitively coupled to receive input signalsfrom a differential amplifier having a pair of inputs which aresymmetrical with respect to ground. The coupling capacitors and the biasresistors of the flip-flop circuit provide a switching threshold whichis smaller during a succession of useful signals and during receipt ofindividual interference signals. The flip-flop circuit feeds impulsegenerating means to provide correctly timed, for example, rectangularsignals.

2 Claims, 3 Drawing Figures CIRCUIT ARRANGEMENT FOR INTERFERENCE- FREERECOGNITION OF THE ZERO CROSSINGS OF SINE-LIKE SIGNALS DESCRIPTION Thisinvention relates to a circuit arrangement for recognition of zerocrossings of sine-like useful signals of variable amplitude andfrequency to produce a timing signal at a zero crossing, and moreparticularly to such a circuit arrangement which is not responsive tointerference signals.

The determination of zero crossings of received signals often poses aproblem during the transmission of data. Such a problem may arise, forexample, during the sensing of information in a directional timedwriting for application onto tapes. In this type of application, atiming signal must be produced at the time at which a sensing signal ispresent, and this timing signal must be derived from the sensing signal.In a typical installation, information to be recorded on a magnetic tapeis received in the form of a succession of generally rectangularsignals. This information is sensed by a sensing head to provide asignal track of substantially sinusoidal form which is provided to adifferentiating circuit by way of a preamplifier in the formation oftiming signals. Sensing pulses are then to be formed during the zeropassage of the differentiated signals, which pulses are preferred tohave a rectangular shape.

It is the primary object of the present invention to determine the zerocrossings of sine-like or sine-shaped signals as accurately as possible.

This objective is realized through the utilization of a differentialamplifier which has a pair of inputs to which the information signalsare applied. A detector circuit having inputs connected to the outputsof the differential amplifier is provided with a switching thresholdwhich is smaller in the presence of a succession of useful informationsignals than in the presence of individual interfering signals. Thedetector circuit provides, on separate outputs, signals which areinverted with respect to one another. These inverted signals are appliedto respective inpulse generators to produce correctly timed impulses.

Other objects, features and advantages of the invention, itsorganization, construction and operation will best be understood by thefollowing detailed description of an exemplary embodiment thereof takenin conjunction with the accompanying drawings, in which:

FIG. 1 illustrates a plurality of waveforms normally found in theprocess of producing timing signals in response to the zero crossings ofdata signals;

FIG. 2 is a schematic block diagram of a circuit arrangement constructedin accordance with the principles of the present invention; and

FIG. 3 is a schematic circuit diagram of the detector circuit of FIG. 2specifically illustrating a flip-flop circuit which is adapted toreceive input signals by way of coupling capacitors.

Referring to FIG. 1, the normal process is illustrated by a plurality ofwaveforms in which line (a) illustrates the information which is to berecorded on a magnetic tape. This information is sensed by a sensinghead which produces a signal track corresponding to line (b). Thesensing signals are applied to a differentiating circuit by way of apreamplifier and the output signals thereof are illustrated in line (c).Sensing pulses are to be formed from the aforementioned signals duringthe zero crossings thereof. The sensing impulses are illustrated inlines (d) and (e). These pulses are then further processed by a timingand decoding circuit.

Referring to FIG. 2, a block diagram of the circuit arrangementaccording to the present invention is illustrated as comprising adifferential amplifier DV, a detector circuit DS and two impulsegenerators I1 and I2. The information signals whose zero crossings areto be determined, and furthermore interference signals, are supplied tothe differential amplifier DV at its inputs El and E2. All of thesesignals, the information and interference signals, may be referred to asinput signals. The two outputs of the differential amplifier DV areconnected to the detector circuit DS which has a pair of switchingthresholds depending on whether a succession of useful signals orindividual interfering signals are present as input signals. In thefirst case, the switching threshold is low so that a useful signal isprocessed even if it is of low amplitude. In the second case, theswitching threshold is high so that even those interfering signals witha larger amplitude do not produce output signals at the detector circuitDS. The two outputs A and A of the detector circuit D8 are provided withoutput signals which are inverted with respect to one another and areconnected to respective impulse producing stages I1 and I2. The timingsignals are then provided at the outputs of the stages I] and I2 andmay, for example, be rectangular type pulses.

The detector circuit DS may comprise a bistable flipflop circuit FFincluding a set input S which is connected to one of the outputs of thedifferential amplifier DV by way of a capacitor C1, and with a resetinput R which is connected with the other output of the differentialamplifier DV via a further condenser C1.

In FIG. 3, an embodiment of a bistable flip-flop circuit FF isillustrated which is of a type well known in the art except for theprovision of the capacitors C1, C1. Inasmuch as this type of flip-flopcircuit is common, it will not be described in detail herein. It hasbeen assumed, for example, that the transistor T is conductive and thetransistor T' is blocked. Thus, a voltage which correspondssubstantially to the supply voltage U, is available at the collector ofthe transistor T'. A positive voltage is provided to the base of thetransistor T by way of a voltage divider circuit R2, R3, so that thetransistor T remains conductive and that a voltage of, for example,about 0.7 volts, is provided at its base. (This is the remaining voltageof the base-emitter diode of the conductive transistor). This directvoltage is also applied to the capacitor C1 at the upper terminalillustrated in the drawing and which is connected to the flip-flopcircuit FF. The base of the transistor T is kept at approximately 0volts by a voltage divider circuit R2,

R3. The transistor T remains blocked and the condenser Cl is dc-wisealso at zero volts at the terminal thereof which is connected to thebase of the transistor T of the flip-flop circuit FF.

The interferences which arrive by way of the signal lines can flip thebistable flip-flop circuit FF only under certain conditions. If oneproceeds from the fact that no interfering signals are coupled in on thelines between the difi'erential amplifier DV and the bistable flip-flopcircuit FF, two kinds of interferences can be differentiated:

l. All interfering signals which are coupled in-phase into theground-symmetrical signal lines at the input of the differentialamplifier DV are eliminated by the push-push suppression of thedifferential amplifier DV. The bistable flip-flop circuit FF thereforecannot be controlled on both inputs simultaneously with setting orresetting pulses of equal polarity.

2. Coupled-in interferences on only one of the signal lines just likeinterferences which are coupled in-phase and in opposition on bothinputs, cause in-phase opposed interfering signals at the outputs of thedifferential amplifier DV. These interfering signals, however, can onlythen flip the bistable flip-flop circuit FF when they appear at theoutput of the differential amplifier DV as positive pulses which areapplied to the blocked transistor of the bistable flip-flop circuit FF.Furthermore, the interference must exceed the switching threshold of thebistable flip-flop circuit which is, for example, 0.7 volts.

A block of information which is recorded on a magnetic tape comprisesthe signal succession itself and a succession of synchronization signalspreceding and following the information signals. These synchronizationsignals exceed the switching threshold, for example 0.7 volts, severaltimes so that the following recorded information can safely berecognized. lf the switching threshold is exceeded several times, notthe O and 0.7 volts, but an average dc value of about 0.35 volts occursat the base connected terminals of the capacitors Cl and Cl due to therepeated flipping process. In order to further flip the bistableflip-flop circuit FF, the sensing signal now only requires an amplitudeof somewhat more than 0.35 volts, i.e. the switching threshold of thecircuit is smaller during the time in which the useful signal is appliedthan during a transmission break. The two switching thresholds may beadjusted with respect to the desired amplitude in values of percentagethereof by the magnitude of the reaction (feedback) resistors R2 and R2of the bistable flip-flop circuit FF. The capacitor C2 and C2 compensatethe input capacitances of the transistors T and T of the bistableflip-flop circuit FF.

When input signals are applied, there are two inphase and opposedrectangular oscillations available which have their flanks at the timelocations of the zero crossings of the input signals. In furtherprocessing, these flanks can be applied to an impulse generator such asa differentiating member or a monostable multivibrator circuit.

The circuit arrangement according to this invention has the followingadvantages:

1. The switching threshold of the circuit arrangement is independent ofthe signal frequency in the operational range. Signal successions ofvarious frequencies, thus also the sensing signals of tape recorders ofdifferent tape speeds, can be processed.

2. The exact times at which the timing signals are provided do notdepend on the amplitude of the input signals. Therefore, input signalswhich are a few percent of the desired amplitude will still be evaluatedcorrectly.

3. The circuit arrangement does not react to interference impulsesduring a transmission break while no useful signals are applied to theinput; therefore, no

false timing pulses are produced.

4. The timing pulses may have a constant width and flank steepness.

5. The circuit arrangement may be provided at a low cost.

Although we have disclosed our invention herein by reference to aspecific illustrative embodiment thereof, many changes and modificationsmay become apparent to those skilled in the art without departing fromthe spirit and scope of our invention, and it is to be understood thatwe intend to include within the patent warranted hereon, all suchchanges and modifications as may reasonably and properly be includedwithin the scope of our contribution to the art.

What we claim is:

l. A circuit arrangement for interference-free recognition of zerocrossings of sine-like useful signals of varying amplitude andfrequency, preceded by a succession of synchronizing pulses, forproducing a timing signal in response to a zero crossing, comprising: adifferential amplifier including a pair of inputs for receiv ing saidsynchronizing pulses and said sine-like signals and a pair of outputs; adetector circuit including a pair of inputs connected to respective onesof the outputs of said differential amplifier, a pair of outputs, andmeans for establishing a switching threshold in response to saidsynchronizing pulses which is smaller in the presence of a succession ofuseful signals than in the presence of individual interference signals,said detector circuit operable to provide timing pulses at said detectorcircuit outputs in response to the zero crossings of a signal applied tothe inputs of said differential amplifier during the lower switchingthreshold; and a pair of pulse generators connected to respective onesof the outputs of said detector circuit.

2. The circuit arrangement according to claim 1, wherein said detectorcircuit comprises a bistableflipflop circuit having a set input and areset input, a first capacitor connected between said set input and oneof said outputs of said differential amplifier and'a second capacitorconnected between said rest input and the other of said outputs of saiddifferential amplifier.

i i 1B i l

1. A circuit arrangement for interference-free recognition of zerocrossings of sine-like useful signals of varying amplitude andfrequency, preceded by a succession of synchronizing pulses, forproducing a timing signal in response to a zero crossing, comprising: adifferential amplifier including a pair of inputs for receiving saidsynchronizing pulses and said sine-like signals and a pair of outputs; adetector circuit including a pair of inputs connected to respective onesof the outputs of said differential amplifier, a pair of outputs, andmeans for establishing a switching threshold in response to saidsynchronizing pulses which is smaller in the presence of a succession ofuseful signals than in the presence of individual interference signals,said detector circuit operable to provide timing pulses at said detectorcircuit outputs in response to the zero crossings of a signal applied tothe inputs of said differential amplifier during the lower switchingthreshold; and a pair of pulse generators connected to respective onesof the outputs of said detector circuit.
 1. A circuit arrangement forinterference-free recognition of zero crossings of sine-like usefulsignals of varying amplitude and frequency, preceded by a succession ofsynchronizing pulses, for producing a timing signal in response to azero crossing, comprising: a differential amplifier including a pair ofinputs for receiving said synchronizing pulses and said sine-likesignals and a pair of outputs; a detector circuit including a pair ofinputs connected to respective ones of the outputs of said differentialamplifier, a pair of outputs, and means for establishing a switchingthreshold in response to said synchronizing pulses which is smaller inthe presence of a succession of useful signals than in the presence ofindividual interference signals, said detector circuit operable toprovide timing pulses at said detector circuit outputs in response tothe zero crossings of a signal applied to the inputs of saiddifferential amplifier during the lower switching threshold; and a pairof pulse generators connected to respective ones of the outputs of saiddetector circuit.